This invention is related to testing of electronic systems.
In the circuit design of many systems, and particularly interconnections between circuit modules (such as two or more circuit boards interconnected via connection terminals on a backplane or through a cable), significant efforts are made to efficiently facilitate operational testing of the connections. Operational testing refers to the testing of the interconnections to determine whether there are shorts or opens. Simply, operational testing consists of sending a test signal from one circuit module to another and determining whether the signal received is the same as the signal that was sent.
Typically, such a method of testing the interconnections between circuit boards would be facilitated by a test module placed on each board. These modules incorporate 1) the software necessary to perform the test, 2) a control (or time synchronization) unit, 3) memory, and 4) a method for communicating with the tester. Once a command signal to initiate the test is received by the test module, the control unit then synchronizes itself with test modules on other circuit boards and begins the test to detect and diagnose possible faults.
In order to test the interconnection between systems on a board for every possible fault, it is necessary to transmit and receive a test signal (hereafter called a "test vector") for all states at which the set of interconnection paths has a single connection at logic level "1". This procedure is at the heart of the test and consumes the most time.
One prior art algorithm which generates a set of test vectors is called a walking-enable algorithm (sometimes called a `walking-one` algorithm) and has driven several other testing mechanisms, such as those described in U.S. Pat. No. 5,107,501 issued on Apr. 2, 1990, U.S. Pat. No. 5,257,268 issued on Mar. 22, 1990, and U.S. Pat. No. 5,305,328 issued on Oct. 22, 1990.
The standard walking-one algorithm is very simple. It generates a test vector with N-number of bits (with N equal to the number of connection paths to be tested) and changes each from logic 0 to logic 1 and back again, one at a time. The problem with this process is that it requires many steps. However, after analyzing each signal received as a result of applying a test vector, it is possible to detect shorts or opens. For example, if a 3-bit test vector sent as 001, but was received as 000, one would determine that the third connection path was either open or shorted to ground ("stuck-at zero"). Similarly, a test vector sent as 000, but appearing as 001, would indicate that the third connection path is shorted to the power supply ("stuck-at one").
Another fault that can be detected using this method is a short between two connection paths. For example, a test vector sent as 001 but received at 011 would indicate that the second and third connection paths are shorted to each other.